1. Field of the Invention
The present invention relates to a technology for displaying delay analysis results.
2. Description of the Related Art
In recent years, with the minimization of integrated semiconductor circuits, the effect of statistical factors such as processing variation, source voltage reduction, and crosstalk has increased, thereby magnifying circuit delay fluctuations. In conventional static timing analysis (STA), although ample delay margin is secured for these circuit delay fluctuations, timing design is becoming more difficult with expanding delay margins.
Hence, needs are rising for statistical static timing analysis (SSTA) that can reduce unnecessary delay margin by precisely determining statistical factors. As a method to estimate circuit delay using SSTA, the following method has been disclosed.
Variation of gate dimension layout is computed based on variation of a gate dimension either variable or non-variable with predetermined values of gate length and gate width of a transistor. Variation is also computed for the processing of gate dimension that correlates to dopant fluctuations. The circuit delay is estimated using information concerning these variations of gate dimension (see, for example, Japanese Patent Application Laid-Open Publication No. 2005-079162).
By the conventional technique, however, an analysis result obtained by SSTA may not give enough information to understand which path or circuit element of the circuit was affected and how, in terms of the delay of the entire circuit.
For example, without supplementary information, determination of delay dispersion characteristics or a bottleneck circuit element only from a result of numerated values or the like was difficult causing problems such as increased design load and a prolonged design period.
Dispersion of delay by statistical factors is difficult to automatically estimate by SSTA. For example, even if delay of a critical path is reduced by 10 picoseconds (ps), delay of the entire circuit is not expected to directly be reduced by 10 ps.
Therefore, SSTA requires manual circuit modification for timing optimization while taking statistical factors into account. Thus, in the design field, an analysis tool that enables a user to interpret analysis results to estimate circuit delay by SSTA is desirable.